1. Technical Field
Various embodiments generally relate to a semiconductor integrated circuit device, more particularly, to a semiconductor integrated circuit device regarding the detection of degradation.
2. Related Art
When a high electric field is applied to gates of PMOS transistors in a semiconductor memory device for a long time, a negative bias used in the semiconductor memory device may be destabilized in accordance with a change in temperature. This may be referred to as negative bias temperature instability (NBTI). The NBTI may cause a threshold voltage of a PMOS transistor to increase. This increase may cause the capacity of the semiconductor memory device to deteriorate.
How much the PMOS transistor has degraded may be obtained by applying a voltage to a gate of an inverter that includes the PMOS transistor and an NMOS transistor. Then a voltage outputted from the inverter may be measured to obtain if the PMOS transistor has been degraded.
However, the output voltage from the inverter may indicate degradation of the NMOS transistor as well as a degradation of the PMOS transistor. Thus, it may be required to separately measure the degradation pertaining to the PMOS transistor and the degradation pertaining to the NMOS transistor.
Further, a large amount of stress may be induced on the NMOS transistor caused by an alternate current (AC) voltage. Thus, it may be required to check the amount of stress caused by a direct current (DC) voltage and the AC voltage.